1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as "semiconductor IC device") internally provided with a logic circuit and a memory circuit. More specifically, the present invention relates to a method of producing mask pattern data when designing circuit patterns for a semiconductor IC device, and an apparatus for carrying out the same method.
2. Description of the Prior Art
Demand for high-performance, low-power-consuming, compact semiconductor IC devices capable of advanced data processing operations for digital signal processing has increased in recent years. A recently proposed semiconductor IC device with built-in DRAM, one of the above-mentioned semiconductor IC devices, is provided with a random logic circuit and a dynamic random access memory circuit (referred to as "DRAM circuit") formed on a semiconductor substrate
In the DRAM circuit, the substrate potential of an N-type MOS transistor forming part of a memory cell is a negative potential of, for example, about -1 V for stabilization through the enhancement of resistance to external noise. (Hereinafter, N-type MOS transistors charged at a negative substrate potential including the foregoing N-type MOS transistor will be generally designated as memory side N-type MOS transistors.) The substrate potential of N-type MOS transistors included in the random logic circuit is charged at a ground potential not to obstruct the enhancement of operating speed. (Hereinafter, such a transistor will be designated as logic side N-type MOS transistors.)
If a P-type semiconductor substrate (hereinafter referred to simply as "P-type substrate") on which the DRAM circuit and the random logic circuit are formed is charged at a negative potential the same as the substrate potential. of the memory side N-type MOS transistors to stabilize the memory side N-type MOS transistors, the substrate potential of the logic side N-type MOS transistors must be electrically isolated from the P-type substrate.
In such a case, the logic side N-type MOS transistor is formed in a P-type well region (hereinafter referred to as "P-type well "), and the P-type well and the P-type substrate are electrically isolated by an N-type well potential isolation region (hereinafter referred to as N-type isolation region").
When designing such a semiconductor IC device with built-in DRAM by autoplacement and autorouting techniques, the layout of the N-type isolation regions must be determined by manually operating a mask pattern data producing apparatus (also called layout editor), namely, a circuit designing computer, after designing the random logic circuit and the DRAM circuit by autoplacement and autorouting techniques because information about the N-type isolation region does not include logical information describing the operations of the random logic circuit.